features ? monolithic field programmable syst em level integrated circuit (fpslic ? ) ? at40k sram-based fpga with embedded high-performance risc avr ? core, extensive data and instruction sram and jtag ice 5,000 to 40,000 gates of patented sram-based at40k fpga with freeram ? ? 2 - 18.4 kbits of distributed single/dual port fpga user sram ? high-performance dsp optimized fpga core cell ? dynamically reconfigurable in-system ? fpga configuration access available on-chip from avr microcontrolle r core to support cache logic ? designs ? very low static and dynamic power consumption ? ideal for portable and handheld applications patented avr enhanced risc architecture ? 120+ powerful instructions ? mo st single clock cycle execution ? high-performance hardware mult iplier for dsp-based systems ? approaching 1 mips per mhz performance ? c code optimized architecture with 32 x 8 general-purpose internal registers ? low-power idle, power-save and power-down modes ? 100 a standby and typical 2-3 ma per mhz active up to 36 kbytes of dynamically allocated instruction and data sram ? up to 16 kbytes x 16 internal 15 ns instructions sram ? up to 16 kbytes x 8 internal 15 ns data sram jtag (ieee std. 1149.1 compliant) interface ? extensive on-chip debug support ? limited boundary-scan capabilities accord ing to the jtag standard (avr ports) avr fixed peripherals ? industry-standard 2-wire serial interface ? two programmable serial uarts ? two 8-bit timer/counters with separate prescaler and pwm ? one 16-bit timer/counter with sepa rate prescaler, compare, capture modes and dual 8-, 9- or 10-bit pwm support for fpga custom peripherals ? avr peripheral control ? 16 decoded avr address lines directly accessible to fpga ? fpga macro library of custom peripherals 16 fpga supplied internal interrupts to avr up to four external interrupts to avr 8 global fpga clocks ? two fpga clocks driven from avr logic ? fpga global clock access available from fpga core multiple oscillator circuits ? programmable watchdog timer with on-chip oscillator ? oscillator to avr internal clock circuit ? software-selectable clock frequency ? oscillator to timer/coun ter for real-time clock v cc : 3.0v - 3.6v 3.3v 33 mhz pci-compliant fpga i/o ? 20 ma sink/source high-performance i/o structures ? all fpga i/o individually programmable high-performance, low-power 0.35 cmos five-layer metal process state-of-the-art integrated pc-based so ftware suite includ ing co-verification 5v i/o tolerant green (pb/halide-free/rohs compli ant) package options available 5k - 40k gates of at40k fpga with 8-bit microcontroller, up to 36k bytes of sram and on-chip jtag ice at94kal series field programmable system level integrated circuit summary 1138is?fpsli?1/08 note: this is a summary document. a complete document is available on our web site at www.atmel.com .
2 1138is?fpsli?1/08 at94kal series fpslic summary 1. description the at94kal series fpslic family shown in table 1-1 is a combination of the popular atmel at40k series sram fpgas and the high-performance atmel avr 8-bit risc microcontroller with standard peripherals. extensive data and in struction sram as well as device control and management logic are included on this monolithic device, fabricated on atmel?s 0.35 five-layer metal cmos process. the at40k fpga core is a fully 3.3v pci-compliant, sram-based fpga with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port sram, 8 global clocks, cache logic ability (partially or fully reconfigurable without lo ss of data) and 5,000 to 40,000 usable gates. notes: 1. fpslic parts with jtag ice support can be id entified by the letter ?j? after the device date code, e.g., 4201 (no ice support) and 4201j (with ice support), see figure 1-1 . table 1-1. the at94k series characteristics device AT94K05al at94k10al at94k40al fpga gates 5k 10k 40k fpga core cells 256 576 2304 fpga sram bits 2048 4096 18432 fpga registers (total) 436 846 2862 maximum fpga user i/o 96 116 120 avr programmable i/o lines 81616 program sram 4 kbytes - 16 kbytes 20 kbytes - 32 kbytes 20 kbytes - 32 kbytes data sram 4 kbytes - 16 kbytes 4 kbytes- 16 kbytes 4 kbytes - 16 kbytes hardware multiplier (8-bit) yes yes yes 2-wire serial interface yes yes yes uarts 2 2 2 watchdog timer yes yes yes timer/counters 3 3 3 real-time clock yes yes yes jtag ice yes (1) ye s (1) ye s (1) ty p i c a l av r throughput @ 25 mhz 19 mips 19 mips 19 mips operating voltage 3.0 - 3.6v 3.0 - 3.6v 3.0 - 3.6v
3 1138is?fpsli?1/08 at94kal series fpslic summary figure 1-1. fpslic device date code with jtag ice support the at94k series architecture is shown in figure 1-2 . figure 1-2. at94k series architecture at94k40al-25dqc 0h1230 4201j date code "j" indicates jtag ice support ? 5 - 40k gates fpga up to 16k x 8 data sram up to 16k x 16 program sram memory programmable i/o with multiply two 8-bit timer/counters 16 prog. i/o lines i/o i/o i/o 2-wire serial unit up to 16 interrupt lines up to 16 addr decoder 4 interrupt lines jtag ice
4 1138is?fpsli?1/08 at94kal series fpslic summary the embedded avr core achieves throughputs approaching 1 mips per mhz by executing powerful instructions in a single-clock cycle, and allows system designers to optimize power consumption versus processing speed. the avr core is based on an enhanced risc architec- ture that combines a rich instruction set with 32 general-purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code-efficient while achi eving throughputs up to ten times faster than con- ventional cisc microcontrollers at the same cl ock frequency. the avr executes out of on-chip sram. both the fpga configuration sram and the avr instruction code sram can be auto- matically loaded at system power-up using atmel?s in-system programmable (isp) at17 series eeprom configuration memories. state-of-the-art fpslic design tools, system designer, were developed in conjunction with the fpslic architecture to help reduce overall time -to-market by integrating microcontroller devel- opment and debug, fpga de velopment and place and r oute, and complete system co-verification in one easy-to-use software tool. table 1-2. fpslic configuration devices fpslic device fpslic configuration device configuration data spare memory AT94K05 at17lv256 226520 bits 35624 bits at94k10 at17lv512 430488 bits 93800 bits at94k40 at17lv010 815382 bits 233194 bits
1138is?fpsli?1/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support fpslic@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? atmel corporation 2008 . all rights reserved. atmel ? , logo and combinations thereof, everywhere you are ? and others, are registered trade- marks or trademarks of atmel corpor ation or its subsidiaries. microsoft ? , windows ? and windows nt ? are the registered trademarks of microsoft corporation. other terms and product names may be trademarks of others.
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